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Defect mitigation of electronic devices is conventionally achieved using thermal annealing. To mobilize the defects, very high temperatures are necessary. Since thermal diffusion is random in nature, the process may take a prolonged period of time. In contrast, we demonstrate a room temperature annealing technique that takes only a few seconds. The fundamental mechanism is defect mobilization by atomic scale mechanical force originating from very high current density but low duty cycle electrical pulses. The high-energy electrons lose their momentum upon collision with the defects, yet the low duty cycle suppresses any heat accumulation to keep the temperature ambient. For a 7 × 10⁵A cm⁻²pulsed current, we report an approximately 26% reduction in specific on-resistance, a 50% increase of the rectification ratio with a lower ideality factor, and reverse leakage current for as-fabricated vertical geometry GaN p–n diodes. We characterize the microscopic defect density of the devices before and after the room temperature processing to explain the improvement in the electrical characteristics. Raman analysis reveals an improvement in the crystallinity of the GaN layer and an approximately 40% relaxation of any post-fabrication residual strain compared to the as-received sample. Cross-sectional transmission electron microscopy (TEM) images and geometric phase analysis results of high-resolution TEM images further confirm the effectiveness of the proposed room temperature annealing technique to mitigate defects in the device. No detrimental effect, such as diffusion and/or segregation of elements, is observed as a result of applying a high-density pulsed current, as confirmed by energy dispersive x-ray spectroscopy mapping.

 

We report the first experimental demonstration of a vertical superjunction device in GaN. P-type nickel oxide (NiO) is sputtered conformally in 6μm deep n-GaN trenches. Sputter recipe is tuned to enable 1017 cm −3 level acceptor concentration in NiO, easing its charge balance with the 9×1016 cm −3 doped n-GaN. Vertical GaN superjunction p-n diodes (SJ-PNDs) are fabricated on both native GaN and low-cost sapphire substrates. GaN SJ-PNDs on GaN and sapphire both show a breakdown voltage (BV) of 1100 V, being at least 900 V higher than their 1-D PND counterparts. The differential specific on-resistance (RON,SP) of the two SJ-PNDs are both 0.3mΩ⋅ cm 2 , with the drift region resistance (RDR,SP) extracted to be 0.15mΩ⋅ cm 2 . The RON,SP∼BV trade-off is among the best in GaN-on-GaN diodes and sets a new record for vertical GaN devices on foreign substrates. The RDR,SP∼BV trade-off exceeds the 1-D GaN limit, fulfilling the superjunction functionality in GaN.